1. Field of the Invention
The present invention relates to a merged memory with logic (MML) semiconductor device or an embedded semiconductor device that integrates a logic device and a memory device into a single chip. More particularly, the present invention relates to an MML semiconductor device and a method of manufacturing the same which a logic area and a memory area planarized at the same height as planarization resistant patterns.
2. Description of Related Art
The MML semiconductor device or the embedded semiconductor device is a semiconductor device that integrates a logic function to perform signal operations and a memory function to store data. Since the MML semiconductor device has a shorter data transfer time and a lower power consumption than a multi-chip semiconductor device which combines a memory device and a logic device in a single package, it is typically implemented in systems that need high speed, low power, and a small footprint.
However, the MML semiconductor devices are relatively difficult to manufacture compared to other semiconductor devices since two different structures need to be manufactured into a single chip. Logic devices are formed based on various circuits that are composed of a significant number of transistors, via plugs, and signal transfer lines. Logic devices neither require a large number of capacitors, nor large volume capacitors. Thus, the size of capacitors tends to be small. However, semiconductor memory devices not only need a large number of transistors to store data, and but also large-sized capacitors. For example, DRAM devices include large capacitors. Therefore, when manufacturing the MML device that integrates logic devices and memory devices into a single chip, the manufacturing processes for the two types of devices are unlikely to be exchangeable as the methods and steps are different from each other. Therefore, in order to manufacture the MML semiconductor device, manufacturing processes are needed that can be used for the both device regions while achieving process stability. For example, in a process that has non-identical layers for each device capacitor, a height of the memory region may be several thousand Å, whereas the capacitors of the logic region are formed to a height of several hundred Å, or are not formed. A planarization process and a process to form via plugs can be unstable due to the height difference, and this can be a disadvantage when manufacturing the MML semiconductor device.